In recent years, transmission devices of a synchronous network such as SDH (Synchronous Digital Hierarchy) or SONET (Synchronous Optical Network) have been connected via an IP (Internet Protocol) network which is an asynchronous transmission network. In this case, the device clock signals (clock pulses) of the transmission devices connected via the IP network are to be synchronized.
FIG. 1 is for describing an overview of a conventional transmission device and a conventional clock supply device. As illustrated in FIG. 1, an SDH transmission device 11A of station A and an SDH transmission device 11B of station B are connected via an SDH network 15 which is a synchronous network. A clock supply device 12A in station A generates clock signals (clock pulses) and supplies the clock signals to the SDH transmission device 11A, a device 13A, and a device 14A in station A.
The SDH transmission device 11A transmits and receives data with the use of the clock signals supplied from the clock supply device 12A. The clock supply device 12A is, for example, a cesium oscillator that outputs highly precise clock signals, and is positioned as the master clock of the entire SDH synchronous network.
The SDH transmission device 11B extracts clock components from data received from the SDH transmission device 11A, and supplies the clock components to a clock supply device 12B. The clock supply device 12B removes fluctuation components such as jitter components from the received clock signals; generates clock signals that are synchronized with the received clock signals; and supplies the generated clock signals as device clock signals to the SDH transmission device 11B, a device 13B, and a device 14B in station B. Thus, all of the devices in station B operate according to the same clock signals. Accordingly, all of the devices in station A and all of the devices in station B are synchronized.
With the advancement of IP networks in recent years, SDH data is packetized into IP packets for performing data transmission, i.e., IP transmission. One example of a method of synchronizing SDH transmission devices via an IP network is the adaptive synchronization method (see, for example, Japanese Laid-Open Patent Application No. 2007-235217). In the adaptive synchronization method, the devices are synchronized by reporting the difference in clock frequency between the SDH transmission device 11A and the SDH transmission device 11B, and correcting the frequencies.
FIG. 2 is for describing an overview of the adaptive synchronization method. As illustrated in FIG. 2, an IP transmission device 20A operates by receiving master clock signals from a clock supply device 21. An IP transmission device 20B receives clock control data transmitted from the IP transmission device 20A, and operates according to clock signals controlled by the clock control data.
The IP transmission device 20A compares the data received from the IP transmission device 20B via an IP network 22 with the master clock signals, detects the difference in frequency between the received data and the master clock signals, and applies the difference to the clock control signals to be transmitted to the IP transmission device 20B.
If the received data is slower than the master clock signals, the IP transmission device 20A generates cock control data for increasing the frequency, and transmits the generated clock control data to the IP transmission device 20B. If the received data is faster than the master clock signals, the IP transmission device 20A generates cock control data for decreasing the frequency, and transmits the generated clock control data to the IP transmission device 20B.
The IP transmission device 20B generates clock signals according to the received clock control data, and uses the generated clock signals as device clock signals in the IP transmission device 20B itself.
However, in the adaptive synchronization method, the frequency is adjusted by being increased or decreased, and therefore the variation range of the frequency is large. Furthermore, the transmission delay according to the IP network may vary (fluctuate) or packet loss may occur, and therefore the transmission delay may become unstable.
One example of a factor causing variations (fluctuations) in the transmission delay is a change of route in the IP network. FIG. 3 is a schematic diagram illustrating route changes in an IP network. The IP network is constituted by multiple routers (SW). The IP transmission device 20A and the IP transmission device 20B are connected via the routers SW1, SW5, and SW12, as indicated by the thick solid line. The transmission path delay is stable as long as the route is fixed in this state. However, the route may change so as to pass through the routers SW1, SW3, SW7, SW6, SW5, SW10, and SW12 as indicated by the dashed line, due to the convergence of the IP network or occasional failures in the routers. In such a case, the transmission path delay may vary.
In the adaptive synchronization method, the clock signals are periodically controlled, and therefore the quality of the clock frequency may be degraded due to variations in the transmission path delay. For this reason, in a case where the IP transmission device 20A and the IP transmission device 20B are SDH transmission devices, and the frequency variation range is large, it may be difficult to achieve synchronization among all of the devices in stations of an SDH network as described with reference to FIG. 1.
In order to solve this problem, there is the frame synchronization method for periodically transmitting frame synchronization packets that are synchronized with the master clock signals, and performing a statistical process at the device that has received the frame synchronization packets to identify clock signals that are synchronized with the master clock signals.
FIG. 4 is for describing an overview of the frame synchronization method. As illustrated in FIG. 4, an IP transmission device 25A operates by receiving master clock signals supplied from a CLK supply device 26. The IP transmission device 25A transmits packets referred to as frame synchronization packets at, for example, an 8 kHz frequency, to an IP transmission device 25B.
The IP transmission device 25B receives the frame synchronization packets. A clock frequency control unit 27 uses clock signals output from a voltage controlled crystal oscillator (VCXO) 28 included in the IP transmission device 25B to count the periods of the frame synchronization packets. When a certain number of samples are received, the clock frequency control unit 27 performs an averaging process (statistical process) to identify the clock frequency of the sending side, and controls the VCXO 28 to have a clock frequency equal to that of the sending side.
However, as illustrated in FIG. 5, the frame synchronization packets may fluctuate or packet loss may occur in the frame synchronization packets (as indicated by a dotted circle) due to convergence of the transmission path or route changes in the IP network. In this case, as illustrated in FIG. 6, the leading edge and the trailing edge of the reproduced clock signal on the receiving side (the leading edge and the trailing edge are illustrated with plural vertical lines) may change with respect to the clock signal on the sending side. Thus, it is difficult to completely compensate for fluctuations and packet losses so as to reduce the amount of jitter in the reproduced synchronized clock signals, as in the synchronization method of the SDH network illustrated in FIG. 1.
The following two points may be considered as factors causing the above problems. First, it is difficult to compensate for variations in the delay caused by route changes. Second, the VCXO 28 has a large allowable deviation.
When there are variations in the delay that are caused by route changes of the IP network transmission path, the delay time changes even though the clock frequency of the side sending the frame synchronization packets has not changed. Hence, the variation in the delay is not distinguishable from a case where the clock frequency has actually changed. Consequently, the output clock signals include many jitter components. Furthermore, a large number of samples (amount of data) is to be used for eliminating the impact of fluctuations in the IP network transmission path. However, it is time consuming to obtain a large number of samples.
In the frame synchronization method, the results of the averaging process are applied to the control signals for the VCXO 28. Thus, if the frequency variation is large in the VCXO 28 being used, the sample data acquired with the clock signals output from the VCXO 28 may have low precision. If such sample data having low precision is used, the difference in the clock phase between receiving side and the sending side may increase. Conversely, if the sample data is acquired at smaller intervals and the results are applied to the control voltage for the VCXO 28, the clock signals may be affected by fluctuations and packet losses in the transmission path of the IP network, and the clock signals may include many jitter components.
Now, a description is given of a PLL (phase locked loop) circuit. PLL is a circuit method of comparing the clock input phase and the VCXO output phase that are to be synchronized, implementing control so that the phases become equal, and locking the input phase and the output phase.
FIG. 7 is a block diagram of PLL. As illustrated in FIG. 7, a clock input unit 31 outputs clock signals (for example, at an 8 kHz frequency) that are targets of synchronization. The frequency of a VCXO 34 is divided by a frequency dividing circuit 35 so that clock signals are adjusted to an 8 kHz frequency. A phase comparing unit 32 compares the clock signals from the clock input unit 31 and the clock signals from the frequency dividing circuit 35. Generally, when comparing phases, the logical sum of the pulses (OR computation) is obtained. When the frequencies are equal, the computation results will indicate a pulse having a duty cycle of 50%. A filter unit 33 at the next stage is constituted by a low-pass filter, which extracts a direct voltage from the pulse obtained by the computation and uses the extracted voltage as a control voltage for controlling the VCXO 34. The circuit is designed to satisfy an equation of control voltage=(power source voltage/2) when the pulse has a duty cycle of 50%. Accordingly, the output frequency from the VCXO 34 is changed according to the variation in the duty cycle, i.e., changed with the direct voltage of the filter unit 33, so as to have the same phase as the input clock.
The PLL method does not involve the procedure of identifying the input clock frequency and adjusting the input clock frequency. Instead, in the PLL method, the phase difference between the input clock and the output frequency from the VCXO 34 is constantly monitored, and the output frequency from the VCXO 34 is adjusted in accordance with the monitored results (frequency is increased or decreased).
Thus, if the control method is inappropriate, many jitter components may be generated. If the PLL method is applied to the frame synchronization method, fluctuations of the transmission path in the IP network correspond to variations in the input clock frequency. Hence, the duty cycle at the phase comparing unit 32 changes significantly and the control voltage (direct voltage) for the VCXO 34 changes sharply, and consequently, jitter components are generated. Furthermore, when the number of samples is increased for the purpose of minimizing fluctuations in the IP transmission path, and more time is taken for the averaging process, the frequency of the VCXO 34 may not be controlled in fine detail. As a result, clock signals with low precision are output.
When the delay varies due to route changes in the IP network, the delay time deviates by 10 msec at a maximum. This means a large variation in the phase when there are no changes in the frequency of the master station. Thus, a large error may occur in the data accumulated by the averaging process, which may erroneously change the clock frequency.
That is, the problem with the frame synchronization method is that fluctuations in the IP transmission path, particularly delay variations caused by route changes, may not be prevented. As a result, the variation amount of the phase is increased and jitter components are increased.